Electrical Engineering question here. How to increase peak voltage dc square wave.
I have an Electrical Engineering question here. Was hoping perhaps someone could help me with a component i'm not familiar with just yet. How to connect it in this circuit and perhaps even a pin out explanation would be amazing.
Here is my dilemma first of all. I have designed a circuit in multi-sim that creates around a 5hz clock pulse using a voltage divider to cut the 12VDC car battery voltage down to a nominal 5Vdc. I have also used a number of logic gates, And, Nor, and even a Not gate inverter to preform medial logic functions.
The purpose of this circuit is to alert the driver to the presence of a door being opened and the headlamps being left on. The And gate in the circuit is used to distinguish most of this. As when both inputs to an and gate are high the output is therefore high. Or in binary 1*1=1. If for any reason the headlamps are off and the door is open this halts the circuit from alerting. Which is great because there is no constant annoyance and one doesn't misinterpret the alarm as being a simple annoyance. Transistors where also used to create an oscillating visual warning of the alarm being omitted. As well as a pizeo speaker audible alarm. Now herein lies my problem. The pizeo buzzer. If connected to the output of the 555 timer chip the output voltage here is far too low. You can surely hear the clock pulses. The binary function is there. 1,0,1,0. Though the only problem is that since the voltage/current is too low or power to this speaker it is far weaker than it's maximum potential. For example after all the voltage drops through the ic logic gates .7 for silicon. We are left with around a nominal 3.4vdc The speaker emits sound at 3vdc nominal but has a max potential of 20vdc. I understand the 20vdc is an impossible feat. This is because pin/pout or efficiency would have to be in excess of 100 percent which is impossible. However i do gather that there must be a way to raise this current/voltage back to the Vs or source voltage max of 12vdc nominal which would be far louder than 3.4vdc. It is also 50 percent of max meaning it will not only be quite loud but it would also have a very long life span at only 50 percent of max tolerance. Now. All of this in mind. I need a component i can add a square wave clock form to that will also allow me to increase my voltage and current back to their max thresholds but keep that pulse so that the pizeo speaker beeps or chimes.
Thank you for any help in this regard.. Please remember the goal here is to raise voltage or E energy back to the source voltage 12v without stripping the source signal into the speaker. This way it is amplified the peak voltages of the square wave. If anyone knows how to do this and could maybe shoot me a easy to read schematic it would be much obliged. I have considered using the transistors I have as amplifiers. Thought their input voltage is max 6v threshold. Meaning they would likely start on fire from 12Vdc. Also i'm not really familar with the science behind how to build an amplifer. But i surely need a crash course because i really need to finish this and i'm so close. BTW for the record i do have any capacitor i could need, ceramic, any resistor value, some npn transistors at the above mentioned rattings, 2n222 type etc. to-18 to-19 format and a protoboard obviously also have an op amp chip and many j/k flip flop 74ls113.
Alpine-
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Re: Electrical Engineering question here. How to increase peak voltage dc square wav
Originally Posted by CJR238
? I know he'd be able to answer this 
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